Circuit for eliminating the hysteresis effect resulting from time delays inherent intrack-while-scan systems



July 29, 1958 o. H.- KNowL-roN, JR.. 1mm. 2,845,532

CIRCUIT FOR ELIMINATING THE H YSTERESIS EFFECT RESULTING FROM TIME DELAYS INHERENT 1N TRAcx-wH1LEscAN sYsTEMs Filed Feb. 2a. 1955 kl/ea/ Ill/0,51%

in copending applications:

CIRCUIT FR ELIMINATING THE HYSTERESIS EFFECT RESULTHNG FRM T DELAYS IN- HERENT IN. TRACK-WHELE-SCAN SYSTEMS Orin Henry Knowlton, Jr., and Lloyd David Ball, Los Angeles,qCalif., assgnors to Gilfillan Bros. Inc., Los Angeles, Calif., a corporation of California Appiianon February-2s, 195s, serial No. 491,062

sclaims. (ci. 25o-,27)

, This invention relates toa circuit for eliminating the hysteresis` effect resulting from time delays inherent in track-while-scan systems and, more particularly, to a circuit for reducing-or eliminating the error which results in tracking coincidence.' circuits when'a varying scanindicating signal is compared with a liixed scan-position signal to generate a gating signal.

While the inventionmay have a multitude of applications, it is particularly useful in systems where `an y angle signal representing the angular position of a radar scanning beam isrcompared with a signal representing an angular position desired to provide an angle` gating signal.r which may be utilized in a range or angle computingloperation. Systems yof this type are described U. S. patent application Serial No. 265,977 for Range and Angle Tracking of Aircraft Using Angle Gated Video, by Alvin Guy Van Alstyne, tiled January` ll, 1952; and U. S. patent application-Serial No. 492,627 for Velocity Tracking System for Increasing the Range of? Acquisitionl ofy Moving Targets, by Lloydl David Ball et al., iiled March :7, 1955. Tracking errors referred to hereinafter as delays v koccur in these systems due to the generation of stretched video and/or to filtering which may be required to improve the signal-to-noise ratio, as in the system by Ball et al. above. These operations introduce certain time delays with respect to target-indicating'signals which are received, with the result that anyV angle gating signal which is generated occurs too early. Thus effectively an error of is added when theV angle scanning voltage is f increasing andan error of is subtracted when the angle scanning voltage is decreasing. The effect may be referred toherein as a type of hysteresis since the magnitude of the resulting signal is different during in- A. creases from the magnitude of the signal duringdecreases.

kcompensate for the Vearly occurrence of the angle gating signals during the increasing period of 'the scanning signal, where the magnitude of the negative step is .selected to correspond to the change in scanning signal amplitude during the error delay introduced. In a similar manner a positive step signal is provided` during decreasing portions of -the scanning signal so that the scanning signal is effectively delayed by an amount compensating` forthe otherwise early occurrence of an angle gating signal.

The positive and negative compensating step signals are combined with Athe normallyl generated scanning signal. to provide a composite signal which when utilized y injanv angle gatingcircuit provides angle gating signals which are' properly phased with respect to the actual y target ipositions.

i. shown, it will be helpful to consider the generalopera'- Accordingly, it is an object of the presentinvention to providea simple` circuitfor eliminating the hysteresis effect resulting fromtime delays introduced by video stretching and/or filtering circuits.

VAnother object of they invention is to provide a `circuit for modifying scan-indicatinginput signals to compensate for expected errorsdue to-timedelays in the systeml with the normal scanning signal to produce a modified f scanning signal, which zmay be utilized toV provide gating signals positioned intime according to the yerrordelay.

The novel features which are believed to be characteristic of Vthe invention, both' as to its organization and method of operation, together' with further objects and advantages.thereof,',will beV better understood from the following description considered in connection with the accompanying drawings. Itis to be expressly understood, however,L that the drawings are for thepurpose of illustration and description only, and are not intended as adeinition of the limits of the invention.

Fig. -l is a schematic diagram of a-'hysteresis eliminating circuit according. to the present invention; and Fig. la isa `composite set of waveforms indicating Various signals. whichi occur in the circuit of Fig. l during its operation. v Referencel is now made to; Fig. l wherein the basic embodiment o-f the invention is shown in; schematic form with a block diagram indication being provided to indicate the major components. As indicated in Fig. 1, the basic embodiment includes a shaper circuit y which receives .a synchronizing signal A representing the scanning periods of a scanning signal B. vThe time relationship between signals A and B is indicatedoperative to frequency divide the* input signal to provide an output signal C of one-half frequency. The relationship between signals A and C is shown more clearlyin Fig. la.

The output signal C produced Lbycircuit 200 is'applied to a relay switch circuit 300 including a cathode follower stage 310 and a relay 320. Relay switch circuit 300 provides an actuating` control for a signal generator circuit 400 which'provides positive and negative signals in response to switch-close-and switch-opencontrol signals provided' by circuit EHBO.A The step signals produced by circuity 400 are designated as VsignalstD and are also shown in Fig. la. Thestep signals D are then; added to, or combined with, the input signals B in an adder circuit 500. which, produces a composite output signal E formulated toeliminate the expected hysteresis effect in the utilizingv system. i

Before considering the-specic circuitarrangement tion of the invention, reference being made to the general block diagram form of Fig. land the operating Vwaveforms of` Fig. la. Theinputsignal B may be assumed to representan angle voltage signal utilized to represent elevation and azimuth scanning in a system of the type y2,845,532 Patented July 29, 195,8

described in the above mentioned copending application by Van Alstyne. It will be noted that this signal includes two successively increasing scanning signals corresponding to the increasing angles of elevation and azimuth and then includes two successively decreasing scanning signals corresponding to the successively decreasing scans in elevation and azimuth.

Since the change from increasing scan to decreasing scan occurs at one-half the frequency of the scan synchronizing signal A, it is necessary to divide this frequency by two as is accomplished in flip-flop 200. It will be understood, however, that where the alteration between increasing and decreasing scanning functions is accomplished once for each period of synchronizing signal A, the frequency division operation is not necessary. Thus if scanning were performed only in elevation or only in azimuth, synchronizing signal A could be utilized directly to control relay switch 300 and the positive and negative step signals would be varied directly as signal A.

It will be noted that a fixed scan position signal level F is shown in Fig. la where the level of signal F represents a desired scan position. Thus in a normal operation the intersection of the line representing the level of signal F with the varying scan signal B indicates the time that an angle gating signal would be produced. However, it will be noted in Fig. la that this intersection provides gating signals as indicated. It will further be noted that during the period between an input signal and a following delayed input signal, signal B increases in voltage by an amount 'during the increasing portions thereof and decreases in voltage by an amount during decreasing portions thereof. When the signal level F is compared with the modified output signal E, however, it will be noted that the angle gating signals resulting are in phase with the delayed input signals. Thus in this manner the delays introduced in the system of utilization have been compensated for.

Although the invention may assume a multitude of specific forms, a particular arrangement is shown to aid those skilled in the art in practicing the invention. Referring again to Fig. l, it is noted that sharper circuit 100 includes an input load resistor R110 having one end connected to an RC filter circuit 120 and the other end connected to ground. RC lter circuit 120 includes a resistor R120 connected to a capacitor C120 having its other end connected to ground. The junction of resistor R120 and capacitor C120 is connected to the grid of a vacuum tube T130 having its cathode connected to a relay 140, the other input terminal of relay 140 being connected to ground. The anode of tube T130 is supplied with a suitable potential.

Relay 140 is actuated to transfer relay contact 140-1 between potentials of 150 volts and 0 volts, providing a sharply varying output signal which is coupled through a capacitor C150 to ip-op 200. Shaper circuit 100 is also shown as including a capacitor C160 connected to a resistor R160 which is grounded. Capacitor C160 also receives a -150 volt potential through a reset switch, the signal being utilized to reset flip-op 200.

As shown in Fig. ,1, ip-flop 200 may be a conventional circuit, including cross-coupled vacuum tubes T201a and T201b. Since the circuit components of flipflop 200 are symmetrical with reference to tubes T201zz and Tflb, only one-half of the connections will be described, it being understood that the other half is similar.

The anode of tube T201a is connected through a load resistor R202a to a source of suitable potential, indicated to be 150 volts. The anode is also cross-coupled to the grid of tube T2011) through a resistor R203!) connected in parallel to a capacitor C203b. This parallel resistorcapacitor circuit is connected through a resistor R204!) and a common biasing resistor R205ab to a suitable source of negative biasing potential, indicated to be -150 volts.

The output signal derived from the anode of tube T201a is designated as signal C and has a waveform similar to that of signal A except that it occurs at one-half the frequency. Signal C then is applied to relay switch circuit '300, which includes a resistor R301 connected to one end of a potentiometer P301 having its other end connected to a source of suitable negative potential, indicated to be -150 volts, through a resistor R302. The center tap of potentiometer P301 is connected to the grid of a tube 310 which has its current path completed through a relay 320 to ground. The anode of tube T310 is supplied with a suitable positive potential, indicated to be +150 volts.

When relay 310 is actuated, contact 310-1 thereof in signal generator circuit 400 is transferred. It will be noted that circuit 400 includes a poteniometer P401 for providing a plus signal and a potentiometer P402 for providing a minus signal. Potentiometer P401 has one end connected to a resistor R401 which receives a suitable positive potential indicated to be 150 volts. The other end of the potentiometer P401 is connected to potentiometer P402 and to ground.

Potentiometer P402 receives a suitable negative potential, indicated to be 150 volts, through a resistor R402. The center taps of potentiometers P401 and P402 provide the plus and minus signals, respectively.

Thus when relay 310 is actuated, contact 310-1 is transferred from a position receiving the signal to a position where the -lsignal is received. As a result, the output signal D produced by circuit 400 and derived through contact S10-1, varies between two discrete values representing -iand The signal D then is combined with signal B in adder circuit 500 which includes a first resistor R501 receiving signal B and a second resistor R502 receiving signal D, the junction of resistors R501 and R502 providing the composite output signal E.

The following circuit elements may be utilized in the specic embodiment of the invention, illustrated in Fig. 1.

Shaper circuit Resistor R 100k ohms.

Resistor R 100k ohms.

Capacitor C120 .05 microfarads.

Tube T 1/2 section of type 12AU7. Capacitor C 470 micromicrofarads. Capacitor C .0l microfarad.

Resistor R160 l megohm.

Flip-flop 200:

- Tubes T201a, T201b 1/zsection `of type l2AT7.

Resistors R202a, R202b 15k ohms. Resistors R203a, R203b 100k ohms. Capacitors C203a, C203b..0l microfarad. Resistors 1220451, R204b 100k ohms.

From the foregoing description it is apparent that the present invention provides a simple and ecient solution to the hysteresis problem inherentin track-while-scan systems,

While particular circuit techniques have been introduced, it will be understood that the invention is not so limited. In its basic form the invention may employ any of a multitude of types of or delay-correction signal generators; of switching means for presenting the delay-correction signals; and of combining means for add- .I

ing the varing scan-indicating signal of the system with the delay-correcting signals. Suitable variations in structure will be apparent to those skilled in the art.

' What is claimed is: y

' l?. In a system wherein a scan-indicating signal having increasing and decreasing portions varying linearly at substantially thesame rate is compared with a fixed scan-position signal to generate a gating signal, the system having inherent time delays; a circuitv for eliminating the effect of the time delays in generating the gating signal, said circuit comprising: first means for generating constant first and second delay-correction signals having levels corresponding to the amplitude change in the scan- `indicating signal during an interval equal to the time delay to be eliminated, respectively; second means including an output circuit for switching said rst and second vdelay-correction signals to said output circuit during said increasing and decreasing signal portions, respectively, said second means thereby producing a correcting output signal; vand third means for combining the varying scanindicating signal with said correcting outputsignal to produce a composite signal which may be utilized to` f' 1 means includes a relay switching circuit including a transfer contact 'providingsaid output circuit, said relay switching circuit being actuable to` transfer said contact between terminals providing said iirst and second signals in response to an input signal indicating the periods of increasing and decreasing amplitude of said scan-indicating signal.

f 4. The circuit defined. in claim 1 wherein said third `means includes a resistance adder having afirst resistor -for receiving said correctingoutput signal and a second resistor for receiving the varying scan-indicating signal,

resistors providing the junction of said first and second said composite signal.

5. In a system having an inherent time delay for input signals where a scanning signal and a position signal are combined to generate a gating signal for controlfling the utilization of the input signals, Ythe scanning sigi nal having scanning periods of linearly increasing amplitude and periods of linearly decreasing amplitude the length of said periods being substantially greater than the time duration for said gating signal; a circuit for eliminating the hysteresis effect resulting from the time i delay, said circuit comprising: Aa signal generator for producing a -lsignal having an amplitude corresponding to the increasing change in the scanning signal during the time delay, and for producing a signal having an amplitude corresponding to the decreasing change in vthe scanning'signal during the time delay; a switching circuit coupled to said signal generator for receiving said -l--and signals and producing an error-correction output signal having a first level corresponding to said -lsignal during said periods of increasing amplitude and having a second level corresponding to said -6 signal during said periods of decreasing amplitude; and adding means responsive to said error-'correction outl .'putsignal and to the scanning signal forproducing a 6 combined output signal which may be utilized to generate gating signals in phase with the corresponding delayed input signals.

6. In a track-while-scan system wherein a varying scanning signal is employed to represent the instantaneous position of an antenna, said scanning signal being.

compared to a fixed amplitude signal in order to generate an angle gate for the system, said scanning signal being recurrently generated in first and second scanning periods, the scanning signal increasing to a predetermined maximum value during each of said first periods, and decreasing to a predetermined minimum value during said second periods, each of said periods .being suby stantially greater than the period of duration of said angle gate, a circuit for delaying each angle gate to compensate for the delay inherent in the system with respect to signals received through said antenna, said circuit com- Y prising: first and second adjustable signal generators for producing first and second constant signals having amplitudes representing the changes of the scanning signal during an interval corresponding tothe system delay for said first and second periods, respectively; a switching circuit for combining said first and second signals to produce a composite correction signal; and means for combining said correction signal and the scanning signal to produce an output signal which maybe utilized to control the generating of angle gates delayed by an amount corresponding to the time delay inherent inthe system.

7. In the track-while-scan system defined in claim 6 wherein azimuth and elevation scanning is performed through respective antennas, said scanning signal cyclically including two of said first periods for increasing azimuth and elevation scanning, and including two of said second periods for decreasing azimuth and elevation scanning; said circuit vfurther including means for counting every other scanning period to produce a control signals where a scanning signal and a position signal are combined to generate a gating signal for controlling the utilization of the input signals, the scanning signal increasing linearly during-first periods to a predetermined maximum value and decreasing linearly during second periods to a predetermined minimum value; a circuit for eliminating the hysteresis effect resulting from the time delay, said circuit comprising: a signal generator for producing +6 and -6 signals; a switching circuit coupled to said signal generator for receiving said -I- and signals, and for producing an error-correction signal having first level corresponding to said -signal during said first periods and al second level corresponding to said -lsignal during said second periods; and adding means responsive to said error-correction output signal and to said scanning signal for producing a comfbined output signal which may be utilized to control the generating of gating signals in phase with the corresponding delayed input signals.

References Cited in the le ofkthis patent UNITED VASTATES PATENTS 2,540,935 Crane Feb. 6,' 1951 2,571,017 Dempsey et al. Oct.V 9, 1951 2,709,804A Chance et al. May 31, 1955 

